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Beyond PCB Assembly Services, Board Support Package Development

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What is a Board Support Package?

A board support package (BSP) is a collection of essential low level software applications configured for a specific microprocessor and its associated hardware. It supplies the drivers for all the hardware in the system andcontainsa bootloader to initialize the microprocessor and hardware prior to loading the operating system. The package may contain additional low level software to assist the developer in initializing the operating system. The BSP can also include a root file system, and a utility to configure the microprocessor and other hardware.By using PNC to develop the BSP, it will allow them to design around their circuit board fabrication capabilities and process.

Board Support Packages are specific to a family of microprocessors and to a specific operating system.  A typical BSP may contain drivers and initialization code for:

  • Initializing the microprocessor
  • The parallel and serial buses
  • The volatile and nonvolatile memory
  • The display and graphics card,
  • Digital and analog I/O
  • Camera, wireless modules, user input devices etc.

While a BSP for the hardware is the first requirement for developing a product with embedded software, this doesn’t mean that every company developing embedded software needs to develop their own BSP with the drivers for their specific hardware configuration. There are five reasons to let an outside BSP developer like PNC develop the BSP for your embedded application.

1. The BSP supplied by the microprocessor manufacture is an incomplete solution

The microprocessor manufacturer will typically supply a rudimentary BSP with their evaluation board.   This is because manufacturers know that making it easier for the developer to work with the microprocessor is helpful to being selected for the final design and pcb assembly process.   However, the manufacturer’s BSP may not have the drivers for the specific hardware in your design – the only way to ensure a BSP fully supports your hardware design is to have it customized for you.

2. Developing device drivers is a specialized skill

Developing the drivers and initialization code BSP requires detailed knowledge of the microprocessor and its peripheral hardware.  Most developers writing applications running on an OS do not have the requisite expertise to write the hardware driversunderneath that OS.  On the other hand, a group focused only on BSP development like the team at PNC obtains that expertise by working with many hardware platforms every year, and by developing robust tested reference code for common peripherals such as displays and USB ports.

3. A BSP is needed only once for a product

A BSP is needed near the beginning of an embedded software product to allow the developers to work with the target hardware instead of an evaluation PC board or emulation software. Once all drivers are debugged, however, the BSP rarely needs to be touched again except for occasional updates to address hardware end-of-life issues.  This is different than the product’s application, which may see multiple releases over the life of the product.  Since BSP updates are so infrequent it does not make sense for an organization to maintain that highly specialized expertise for the months or years between BSP updates.

4. The BSP and associated drivers are invisible to the customer

Application software that meets customer needs is a close collaboration between developers, product management, marketing, and sales.  Any time spent by the in-house team developing a BSP is time not spent developing features the customer will see and use.  Outsourcing the invisible aspects of the product like the BSP allows the development team to stay focused on the customer.

5. Outsourcing the BSP can accelerate product development

Handing off the BSP to an outside supplier like PNC means that the team’s developers are not tied down developing it internally.  The BSP supplier can develop the BSP incrementally starting with core functionality followed by drivers for some of the less critical hardware once the development team is ready for it.  The outside supplier also brings deep expertise to the driver development, meaning driver development takes less time, and works the first time. The most beneficial reason for PNC to develop your BSP is that they can also fabricate PCB’s as well having in house pcb assembly services.

Talk to the software team at PNC the next time you have a time critical embedded project.  Let PNC help you with your Board Support Package, device drivers, operating systems porting, or protocol stacks development.

PCB Design, Selecting the Right PCB Trace Widths?

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Every PCB designer has a series of decisions to make PCB Design as they translate an abstract schematic into a functional, reliable, and manufacturable PCB assembly. Placing the components on the    PCB is usually the first step, connecting those components with copper conductors to create the circuit is the next.  To connect the components, the layout designer must interpret the circuit netlist and turn that netlist into actual copper traces, subject to constraints of both manufacturing technology and the laws of physics.  One of the most important considerations for the designer is the appropriate trace width for each of those connections. The width of each trace determines both the real-world performance of the circuit and the overall size and number of layers of the PCB.

To balance circuit performance and PCB size, the designer needs to balance four considerations:

  • The manufacturer’s minimum trace width and spacing
  • The size and pitch of the component pads that the trace will connect
  • The amount of current flowing through the trace
  • Whether the trace is part of a controlled impedance circuit

Minimum Trace Width and Spacing

The manufacturer’s minimum trace width and trace spacing will define the smallest trace width that can be used for all signal traces that do not carry significant current or have impedance constraints.  The minimum trace width is typically used as the default for the layout, since using the minimum trace width will result in the smallest possible PCB and the most flexibility in routing.

For a standard Printed Circuit Board, fabrication minimum trace widths/spacing is typically 5 mil (.127mm). PNC’s High Density Interconnect (HDI) PCB trace width/spacing can be as narrow as 3 mils (.076mm)

Trace Width vs Pad Width

Another consideration when selecting trace widths is that the trace should be smaller or equal to the pad width. For the most part, if working with the minimum trace widths, this will not be an issue, however, care must be taken when laying out the traces and pads for high current applications.

High Current Traces

Once a designer has placed the components in the layout, they will often focus next on creating the power and ground traces to the active components.  This is because the current carrying traces need to be appropriately sized and routed.   Signal traces, which are typically at the minimum trace width, can be more easily routed around the larger power traces.

Copper PCB traces, like any conductor, have an internal resistance that is proportional to the conductor length, and inversely proportional to its cross-sectional area. Since the copper on a layer is of a uniform thickness, the width of the trace determines its cross-sectional area.  There will be both a voltage drop along the trace as well as heating of the trace due to the power dissipation.  If a PC Board trace is not sized appropriately to carry the current required by the circuit, the trace can fail due to overheating, or the high voltage drop along the trace can cause intermittent circuit problems as the current and thus the voltage drop in the trace varies over time.

Designers often create an internal copperlayer with multiple buses of various voltages.  Since that layer consists only of power busses, the buses can be quite wide.  The designer will then connect the individual components to the bus using vias rising to the component’s power pins.  A bus based design reduces voltage drop at far from the power supply while reducing the width of the short connector trace to the same size as the component pin pad.

In the days before the internet and sophisticated PCB layout software,  designers would use the pages of current vs trace width tables  in IPC 2152 “Standard for Determining Current Carrying Capacity in Printed Board Design”  Now there are online calculators  based on those tables that take in to consideration all of the factors involved in determining the appropriate trace width for a specific current and allowable temperature rise of the trace due to the power dissipation. Many full featured Printed Circuit Board layout applications have the calculations embedded in their design rules.

If a PCB is intended for high power applications such as motor control or an LED power supply, a copper layer thicker than the typical 1 oz can be used but note that it is difficult to etch fine traces and pads in thicker copper.  Make sure to check with the PCB fabricator about their capabilities. PNC has experience with thick copper layers and can provide advice to the designer about what is possible.

Controlling Trace Impedance

The last consideration in selecting trace widths is the impedance of the trace, which becomes a factor in high frequency signals such asDDR busses, video such as HDMI, and high speed serial communication like USB and Gigabit Ethernet. At these high frequencies, not only the trace resistance, but the capacitance and inductance of the trace become significant factors.

Designing controlled impedance (CI) circuits is beyond the scope of this post, because designing a controlled impedance circuit requires taking into account the dielectric constant of the PCB, the length and routing of the trace in addition to the width of the trace.  However, trace width is one of the most easily controlled elements of impedance controlled circuits,so the trace width on individual controlled impedance circuits may be different from the width of other low frequency signal traces, and those traces may be finetuned after the prototype PCBs are tested.

The design of controlled impedance circuits is described in detail in IPC-2141A “Design Guide for High-Speed Controlled Impedance Circuit Boards”, and many of the formulas are available in online calculators or as options in PCB layout applications. When designing high speed circuits, it also pays to work with a PCB manufacturer like PNC that has expertise in fabricating PCBs with precise and consistent dielectric properties.

Schedule a Design Review with your PCBA manufacturer

 The designers at PNC have experience with both high power and high-frequency RF and microwave PCB layout designs.  Because they work closely with the manufacturing team, they know what is possible to achieve with the thick copper layers used in today’s compact LED and motor controllers,  and they know what it takes to maintain consistent dielectric properties in the substrates, needed for predictable RF performance. Let them help you with your design.

What’s a HDI Printed Circuit Board?

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HDI stands for High Density Interconnect. HDI PCBs have finer traces and trace spacing, laser drilled micro vias and higher connection pad density. Its two chief advantages are that it permits the use of fine pitch BGAs and it reduces the number of PCB layers required because the finer traces and smaller vias allow more circuitry in a smaller area.

Narrow trace widths mean higher circuit density

At PNC standard PC Board fabrication uses a minimum trace width of 5 mil, with a 5 mil space between traces (5/5mil) PNC’s HDI trace widths can be as narrow as 3 mil with 3 mil spacing.  These finer traces allow 160% more traces in the same real estate. 3/3mil spacing will also allow two traces to escape between pads of a standard BGA, meaning less PCB layers are needed to fan out the pins from the BGA.

Microvias are the enabling technology for HDI

Narrow trace widths used in HDI PC Board are a result of the gradual refinement of photolithography and etching technology.  Microvias on the other hand, are a revolutionary innovation driven by the development of high powered lasers that can be controlled accurately enough to ablate a 3 mil hole through the surface layer of copper and underlying laminate, without damaging the underlying layer of copper.

The minimum hole size for PNC’s laser drilled microvias are 3 mil and the minimum pad diameter for the microvia is 7 mil.  Pads for laser drilled holes can be smaller than for mechanically drilled holes because of the location accuracy of the laser drilled hole.  There is no mechanical deflection of the drill bit to account for.  The laser drilled holes can be fully copper filled and planarized flat, so they can be used as pads for fine pitched BGAs with 0.4mm or smaller spacing. Using microvias as pads allows the signal trace to fan out by going straight down and out to an inner layer of the printed circuit board.

The biggest limitation with microvias is the aspect ratio of the holes.  Where a drilled through hole can have a 10:1 depth to diameter aspect ratio, a laser drill can achieve no more than around a 1:1 aspect ratio.  This means that the smallest microvia can only connect two adjacent copper layers. A larger diameter microvia can penetrate two layers. To connect deeper layers, the designer must stack vias one directly atop another.

Laser drilling of the microvias changes the way PCBs are fabricated and gives the designer flexibility that they do not have with through hole vias.  In a standard drilled PCB, via holes are drilled and plated after the PCB fabrication stack-up is completed.  Because the microvias can only bridge two or three copper layers, the microvias must be drilled and plated at each lamination step.  This means that microvias can be fully buried between layers, stacked or staggered to allow the microvia to connect multiple layers of the stack up.

The major space saving advantage of the microvia technology is that vias can just connect traces that need to be connected, rather than taking up real estate all the way through the PCB the way a through hole via does.

The Printed Circuit Board designers at PNC take advantage of this by locating the power and ground layers at the top of the stack up.  Since all active components access power and ground, sometimes through multiple pins, having the power and ground layers directly below the component layer allows all those connections to be made directly by microvias.  This leaves the component layers and layers beneath the power and ground layers completely unobstructed for signal routing. This has the added advantage of reducing parasitic capacitance because it eliminates the circuit stubs caused by plated through holes.

Two sided boards are typically fabricated with a combination of through holes and microvias.   Though holes can be drilled just through the core, connecting the stacks on the top and bottom of the board from the lowest layer, or through holes can be drilled through the entire stack directly connecting the traces on the top and bottom component layers.

 

HDI PCBs are a necessity when using fine pitched BGAs, but they can also reduce cost on PCBs without fine pitched BGAs because of the reduced layer count.  On your next PCB design, talk to the experts at PNC.  They can help you determine if HDI technology is can reduce your PCB cost by reducing layer count and shrinking the PCB size.

PNC’s step by step guide to PCB Design component placement

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A schematic is an abstraction, a representation of an ideal circuit. A PCB Assembly, on the other hand, is a complex mechanical assembly. All the components in the circuit design must fit within the physical boundary of the PCB. The designer must locate and place hundreds of components subject both to the mechanical constraints of the product design and the manufacturing process while not introducing electrical noise into the circuit.

It can seem overwhelming to someone new to the PCB layout process. Fortunately, there are some simple guidelines used by the designers at PNC that will help break the layout task into manageable pieces.

Initial component placement considerations

Start by identifying the mechanical constraints on the component location. The Printed Circuit Board size and shape will be defined by the overall product configuration. Typically, the product’s mechanical design will define the location of the connectors, the keep-out zones and the locations of the heat sinks. The initial mechanical layout of the PCB is often an iterative process defined during design and early prototyping.

One recommended keep-out area is the perimeter of the board. The perimeter should be kept free to give the manufacturer a place to grip the PCB during assembly process, and room to score smaller boards to allow them to be removed from a larger multi-arrayed panel.

PNC recommends that all components be kept .050” from the PCB edge. Taller and more fragile components like capacitors should be kept .125” from the edge if possible, to allow room for tooling access to prevent damage when the PC Board is routed or scored from the panel.

The next step is to divide the PCB into functional modules to simplify routing and grounding. This will help minimize noise between power components, high speed digital components and analog components. Switching power supplies are particularly noisy, so the power supplies and their associated components should be grouped together as far as possible from noise sensitive sections of the circuit. While defining the location of the modules, be aware that high power components will need heat sinks, which may limit placement options.

Locating active components

Once the edge components are placed and functional areas of the Printed Circuit Board are defined, the next step is to locate the BGAs, quad packs and other large high pin count components. The room needed to fan out their pin counts is going to drive the locations of all the components around them.

In general, try to align the active components ICs with the #1 pin or A1 pin in the same orientation. While this may not have any utility in the actual circuit, it will make inspection and debugging of the initial prototypes far less frustrating.

Locating passive components

As a follow on to locating the active components, the bypass or decoupling capacitors on the power pins should be located as close to the IC as practical to minimize the parasitic inductance. If more than one capacitor is being used PNC recommends that the lowest value capacitor should place closest to the power pin. If components will be located on both sides of the PC Board, the bypass capacitors are often located on the opposite side, directly under the power pin. If possible, each power pin should have its own bypass capacitor.

Polarized components such as electrolytic capacitors and diodes should be arranged so they are all facing the same way. During debugging, it is much easier to spot the one diode that is not like the others rather than having to look at the silkscreen of each diode to determine if it is installed correctly.

Pull-up resistors and other groups of identical components are often grouped and lined up to simplify layout, debugging and inspection. Consider using resistor arrays when possible to save board space and reduce component count.

Inductors break this placement guideline. Because inductors generate magnetic fields, placing them too close together, particularly end to end, can cause inductive coupling, changing the value of the inductors.

Layout of double-sided boards

Double sided PCBs, PCBs with components on both sides, are expensive to produce, but may be necessary when real estate on the PCB design is tight, and when the overall product form factor is more important than PCB cost. A double-sided PCB is more expensive because it will need to pass though the pick and place machine and reflow oven twice.
Since the double-sided PCB will need to pass through the reflow oven twice, PNC recommends that the lighter and more heat resistant components be placed on the bottom of the board. Larger components on the bottom of the board will be glued to keep them from falling off, the smaller passive components cannot be glued, but the surface tension of the solder will hold them in place during the second pass through the oven.

Schedule a Design Review with your PCBA manufacturer

These are some general guidelines to aid in component placement used by the PCB designers at PNC. However, they are just guidelines. The best way to ensure that the printed circuit board assembly can be manufactured reliably is to have the layout reviewed by the people who will manufacture it. PNC’s designers can review your design to help reduce production cost and improve yield and reliability. Contact PNC today to schedule a review.

PCB assembly Pre-Reflow FAI

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First article inspection (FAI) prior to SMT assembly is a design verification methodology that provides a reported verification and validation of details of a product on the shopfloor per its manufacturing procedure and requirements. There are various ways to perform FAI, from both supplier’s and customer’s side, making it a very dynamic process. This means that each organization can tailor its FAI method to benefit itself and consequently, its customer, yet maintain rigid performance standards at the same time. FAI involves qualitative and quantitative measurement. FAI is also highly effective since it can potentially fulfill process validation requirements of quality management systems like ISO9001 or AS9100.

In the PCBA manufacturing industry, FAI can be effectively employed in validating materials for manufacture, underlying technologies, manufacturing processes used, packaging, and equipment. It can also be applied to a batch of a given sample-size from a mass-production instead of just the first sample, as the name might suggest. At PNC, strict adherence to our manufacturing standards helps in production with better yield but at the same time, facilitating dynamic validation techniques in our manufacturing process allows us to reduce lead time. The focus of FAI in PNC assembly lies in validating the pcb assembly before reflowing so that the SMT team can make necessary adjustments for the next batch, saving time and effort during rework. They are also responsible for validating the correct loading of the right component in its allotted slot per the assembly program. This extra step helps in validating the placements of the components and improves the turnout rate for a successful production.

All aspects of reflow also must be amenable to improve solder performance and the same translates to our guideline where only the most recent batch of solder paste (with most activity) is permitted for use, which is validated by FAI. Apart from pre-reflow FAI, post-reflow X-Ray also helps validate the solder performance based on the reflow profile which can then be adjusted accordingly so that all components are successfully soldered. This can be similarly implemented at the rest of the printed circuit board assembly stages as well up to testing. But there is a necessity to establish a constant groundwork or point of reference in such a dynamic process to give each validation at a particular stage, the perspective of what changes were made before. This is achieved by using a single piece of documentation used to validate at every stage, wherever applicable, and that document reports any changes made to the processes or product, to the next stage.

pcb_assembly
pcb_assembly

PNC employs the use of AEGIS software to combine SMT assembly guidelines and inspection requirements into a single document (internally referred to as AEGIS). The AEGIS is used to report every single FAI validation to different stages of assembly. PNC’s FAI process for SMT starts with thorough solder paste FAI & its validation, which will be detailed in another post. For this post, let us consider pre-reflow FAI and highlight its validation process since it is the most crucial stage. The procedure is as follows:
1. The SMT team confirms the correct allocation of components as given in the assembly program. This is done by comparing each component with its description, measuring component value wherever applicable, and checking for physical marking on ICs. This helps in validating that the right component has been placed in its respective position on the board.
2. The next step involves checking for the polarity of components, wherever applicable. This is a two-step process. First, the supply angle of a component in the reel needs to be checked and second, the placement of that very component on the PCB needs to be verified.
3. Now, once the first board is assembled, the pcb assembly is put through FAI, where the placements of all components on the board are checked, any necessary placements that remain are placed manually and polarities of applicable components are checked and changed as per what is given in the AEGIS. The same changes are made in the assembly program to avoid the same occurrence in the rest of the batch. Components that are designated as DNP (Do Not Place) are also checked and finally, the solder paste information such as solder type, lot number, date of manufacture, and expiry are checked to ensure that the right solder paste has been used.
4. All these checks translate to notes, remarks, and checks on the AEGIS document, which can then be referred at later stages up to final inspection. If the job in consideration is a repeat job, it can be optimized to avoid any errors made in the first batch of production.
5. The board is then sent through reflow. Once reflowed, the board is extensively inspected under high magnification camera for quality of component placement, solder joints etc. yielded by SMT process.
6. Each section in the AEGIS is meant for FAI by a different team performing a different operation.

PNC has been able to reduce its lead time and increase customer satisfaction significantly and our personalized and successful FAI is a big factor contributing towards it. Further development to the FAI process is underway as much as it is needed to achieve better production yield over time for all the different types of PC Board assembly that are assembled at PNC.