Tag Archives: printed circuit assembly

Importance of Good ESD Practices in SMT Assembly

The management of electrostatic discharge is a crucial feature in the production, assembly, and maintenance of electronic equipment. If electrostatic discharges are not managed, they may destroy an electrical device at any step of its manufacture or use. Grounding any wires that come into touch with or are close to the electrical equipment is the main way of control. Humans, tools, ESD mats, various electronic equipment, boards, connections, packing, and other conductors are among them. Removal of extra insulators, shielding, ionization, pollution regulations, training, awareness, and highest level compliance are all part of a successful ESD management program.

What exactly is ESD?

The quick current flow between two oppositely charged objects generated by the response to an electric short or insulator breakdown is known as electrostatic discharge (ESD). Tribocharging via electrostatic induction may generate a build-up of high voltage. When different-charged items are placed near together, or the dielectric among them disintegrates, ESD develops, which typically results in a vivid spark. This could result in major part damage during the printed circuit board assembly process.

ESD may generate tremendous electric sparks and less dramatic forms, not seen or heard but strong enough for sensitive electrical equipment to be harmed. Electric sparks need a field strength in the air of more than 40 kV/cm, as seen in lightning strikes. Energy transfer from acute electrodes and brush discharge from flat electrodes are two further types of ESD.

Smt assembly
Smt assembly

What is the importance of ESD?

Exposure to ESD, or the abrupt passage of electricity over two electrically charged items, may cause any electronic device or part to deteriorate. When two differentially charged items brush against one other, an apparent spark is typically produced. Even easy movement on a workstation may cause ESD, which may harm a device’s sensitive electrical components. It may also have an impact on the functioning and quality of electrical devices and components. As a result, ESD protection solutions are critical for preventing the accumulation of electrostatic force in electronic devices. Their primary purpose is to limit the possibility of ESD-sensitive equipment being damaged. These protective solutions are particularly successful in preventing system failure and extending the life of fragile electrical devices.

A pro-EPA (ESD protected area) should be established for the safety of production facilities or pcb assembly workstations. EPA may be enhanced using ESD-resistant goods, including workbenches, commercial furnishings, trolleys, warehouses, etc. Wristbands, conductive straps, and other devices may be worn by persons working in the vicinity to safely disperse ESD. These items are wired to the ground, where an electrostatic charge is dissipated via earthing points and connections. This allows ESD to be dissipated more safely.

ESD Protection Zones in the Facility:

Electrostatic Discharge Shielded Locations (EPAs) prevent ESD-sensitive devices from typical electrostatic discharge sources by grounding conductive objects and personnel in ESD-prone production areas such as:

Pro mats, for example, are conductive surface materials.

  • Staff uniforms and clothing with conductive filaments
  • Optimal humidity levels

Circuits with built-in ESD protection:

When assemblies are most susceptible like during electronic assembly, built-in ESD protection decreases the danger of complete circuit breakdown or latent damage. The following are some of the best practices for ESD protection built-in:

  • Choosing the right short backflow prevention device for your Printed Circuit Board
  • Installing the isolator at the ESD contact site

What is ESD (Electronic Stability Device) Training?

Controlling electrostatic discharge requires ESD training. You recognize the significance of avoiding electrostatic discharge. You already know that in electronics assembly, an ESD control program is critical for quality and yield. Any successful ESD control program and vital to successful electronic manufacturing require an effective, systematic, and long-term ESD training, certification, and re-certification system.

What is ESD 20.20 Training?

Electro Static Discharge (ESD) is a typical phenomenon in which a person or almost any ‘charged’ item emits a brief electrical shock.

The multi-industry guideline for developing ESD management programs that safeguard today’s highly sophisticated electrical parts, assemblies, and machinery from expensive ESD damage and decrease downtime is ANSI/ESD S20.20. An organization may design an ESD control program that protects equipment down to 100 volts or fewer using the format’s control techniques and advice.

The S20.20 standard, which several multinational OEMs use and serve as a successor for MIL-STD 1686, has swiftly gained traction in the electronic, telecommunications, aircraft, automotive, and devices sectors. In reality, the S20.20 standard is included in the telecom industry reference TL 9000 as a recommended practice for addressing ESD control requirements.

A good ESD management program within a printed circuit board assembly facility may help you avoid expensive system failures while also improving customer service. Organizations may use NQA’s ESDA-accredited Site Certification program to guarantee that their programs satisfy the standards and give documentation of conformance for customer marketing reasons.

When it comes to ESD training, there’s a statement that goes something like this:

“Managing an ESD program is an important aspect of a full quality program in the modern electronics sector. Any electronics company that does not have an active ESD program is putting itself or its customers in danger.”

At PNC, all the employees receive annual ESD training based on ESD 20.20.

What Are the Advantages of ESD Training?

Improper handling of today’s electrical components may quickly harm or make them faulty. Furthermore, rejecting or fixing items affected by electrostatic discharge (ESD) may waste time and money for companies that handle electronic components.

  1. Raises ESD awareness in the workplace
  2. Enhances overall performance levels and product control
  3. Lowers the failure rate, lowers rework, and saves money.
  4. Aligns with peers in the electronics industry
  5. Provides consumers with clear evidence during site visits
  6. Controls for ESD (proper clothing, grounded tables, signage, etc.)
  7. Increases marketability and gives you a competitive edge.

What is ESD Audit?

A solid ESD control program should include an ESD audit. It audits all ESD-control processes and products, reminds employees of their obligations regularly, and provides management with the information needed to take remedial action.

An audit is conducted using an ESD control program that has been designed, authorized by management, and applied at all levels of the smt assembly area. In most cases, such software is based on industry-developed standards. ANSI/ESD S20.20-1999, produced and regulated by the ESD Association, is the cost of setting up a document for many programs and is a good option for a guiding standard.

ESD Audit Work Area:

The audit must ensure that the border between ESD-protected and non-ESD-protected locations is properly marked, e.g. signs, directional arrows, and floor markings. This reminds both employers and employees that they enter a critical control environment or leave it.

Supply carts to store or carry ESD-sensitive items should have electrically linked uprights and shelves mounted by a trailing chain to avoid tribo-loading. A floor snap is strongly suggested for strong grounding of the cart when fixed in an ESD safe location.

ESD Practices at PNC Online                           

During an audit at PNC, it was noted that all the employees themselves tested multiple times a day. The company follows all standard patterns for complete ESD audits on an annual basis. PNC employees wear ESD Smocks, wrist straps, foot Straps, and ESD shoes.

Minimizing Crosstalk in PC Board Layout

In this ongoing series on PCB layout from the design team at PNC, previous posts have looked at some of the initial steps to turn a circuit schematic into a manufacturable, reliable PCB. These posts have looked at  component placement, selecting appropriate trace widths, and BGA routing.   In this post we are going to take a deeper dive into methods for reducing crosstalk in the PCB design. After the power and ground have been routed, the next task is to route high speed signal traces, and the traces that could either generate or receive crosstalk.

 What is Crosstalk?

Crosstalk occurs when the signal on an aggressor trace on a PCB appears on a nearby victim trace, due to capacitive and inductive coupling between the two traces.  Typical aggressor signal traces are:

● High speed digital signals, especially clock signals
● Noise from switching power suppliers
● High frequency RF.

Victim signal traces, on the other hand, carry high impedance signals like op amp input lines or reset lines, or low impedance signals with long loops.   Low amplitude signals such as a sensitive analog measuring circuit traces are also susceptible.

Crosstalk occurs when aggressor trace and victim trace are close together and run in parallel for a distance.  The aggressor and victim(s) can be side to side on the same layer or on top of each other on adjacent signal layers. Coupling between traces on adjacent layers separated by just a thin section of laminate is called broadside coupling.

Minimizing Crosstalk in PC Board Layout
Minimizing Crosstalk in PC Board Layout

 

 

 

 

 

Printed Circuit Board Design guidelines to reduce crosstalk

There are several design rules to reduce crosstalk between signal traces.  Before applying these rules, the first step is to use the general guidelines described above to identify and flag any potential aggressor signal traces and their potential victims.

Since crosstalk occurs between two traces running in parallel, try to reduce the distance that the aggressor and victim traces run in parallel. Unfortunately, this may be difficult if the signals originate and terminate from the same locations.  To minimize broadside coupling try to orient the signal traces east-west on one layer and north-south on the second layer.

It is essential to have a broad contiguous ground plane directly under (or over) the signal layer.  A ground plane located between two signal layers can prevent broadside coupling. However, make sure that ground planes located on adjacent layers but not electrically connected do not overlap.  The overlapping ground planes separated by a dielectric form a capacitor, which can transmit noise from one ground plane to the other. This can defeat the purpose of separate ground planes if they were created to isolate the noisy elements of a circuit from the noise sensitive ones.

Increasing trce spacing

The most effective method of reducing crosstalk is to increase the spacing between the aggressor signal trace and the potential victim traces.  Like all electromagnetic radiation, electrical or magnetic coupling between the two traces drops with the square of the distance between them.  The amount of spacing required between the traces is dependent on the height of the traces above the ground plane.   The formula defining this relationship is from Douglas Brooks “Crosstalk Coupling: Single-Ended vs. Differential”   The coupling between two traces is proportional to:

Where S is the spacing between traces, and H is the distance from the trace to the ground plane.  Once H is defined by the lamination stack-up, the relative change in coupling can be easily plotted as a function of S.  Douglas Brooks looks in detail at the coupling between traces under several scenarios.  For those looking for some general guidance, a spacing of 5H is considered conservative.  The PC Board design team at PNC can assist designing a PCB stack up that will minimize the spacing needed between coupled traces, ensuring that crosstalk is minimized while maintaining routing density.

Finally, for very high speed digital signal traces, consider the use of differential pairs.  For many designers, the most common applications for a differential pair is for a high speed serial bus like USB, SATA, or HDMI.  The design rules for the layout of differential traces is beyond the scope of this post.

The most important part of reducing crosstalk in your PCB design is to first recognize in which signal traces crosstalk is likely to occur, then follow the guidelines above to minimize it.  PNC’s Printed Circuit Board designers have experience with high speed digital and RF circuits and can help you select the correct PCB layer stack-up and review your designs for areas where crosstalk is likely and suggest ways to minimize it. Request a design review from PNC today

PCB assembly Pre-Reflow FAI

First article inspection (FAI) prior to SMT assembly is a design verification methodology that provides a reported verification and validation of details of a product on the shopfloor per its manufacturing procedure and requirements. There are various ways to perform FAI, from both supplier’s and customer’s side, making it a very dynamic process. This means that each organization can tailor its FAI method to benefit itself and consequently, its customer, yet maintain rigid performance standards at the same time. FAI involves qualitative and quantitative measurement. FAI is also highly effective since it can potentially fulfill process validation requirements of quality management systems like ISO9001 or AS9100.

In the PCBA manufacturing industry, FAI can be effectively employed in validating materials for manufacture, underlying technologies, manufacturing processes used, packaging, and equipment. It can also be applied to a batch of a given sample-size from a mass-production instead of just the first sample, as the name might suggest. At PNC, strict adherence to our manufacturing standards helps in production with better yield but at the same time, facilitating dynamic validation techniques in our manufacturing process allows us to reduce lead time. The focus of FAI in PNC assembly lies in validating the pcb assembly before reflowing so that the SMT team can make necessary adjustments for the next batch, saving time and effort during rework. They are also responsible for validating the correct loading of the right component in its allotted slot per the assembly program. This extra step helps in validating the placements of the components and improves the turnout rate for a successful production.

All aspects of reflow also must be amenable to improve solder performance and the same translates to our guideline where only the most recent batch of solder paste (with most activity) is permitted for use, which is validated by FAI. Apart from pre-reflow FAI, post-reflow X-Ray also helps validate the solder performance based on the reflow profile which can then be adjusted accordingly so that all components are successfully soldered. This can be similarly implemented at the rest of the printed circuit board assembly stages as well up to testing. But there is a necessity to establish a constant groundwork or point of reference in such a dynamic process to give each validation at a particular stage, the perspective of what changes were made before. This is achieved by using a single piece of documentation used to validate at every stage, wherever applicable, and that document reports any changes made to the processes or product, to the next stage.

pcb_assembly
pcb_assembly

PNC employs the use of AEGIS software to combine SMT assembly guidelines and inspection requirements into a single document (internally referred to as AEGIS). The AEGIS is used to report every single FAI validation to different stages of assembly. PNC’s FAI process for SMT starts with thorough solder paste FAI & its validation, which will be detailed in another post. For this post, let us consider pre-reflow FAI and highlight its validation process since it is the most crucial stage. The procedure is as follows:
1. The SMT team confirms the correct allocation of components as given in the assembly program. This is done by comparing each component with its description, measuring component value wherever applicable, and checking for physical marking on ICs. This helps in validating that the right component has been placed in its respective position on the board.
2. The next step involves checking for the polarity of components, wherever applicable. This is a two-step process. First, the supply angle of a component in the reel needs to be checked and second, the placement of that very component on the PCB needs to be verified.
3. Now, once the first board is assembled, the pcb assembly is put through FAI, where the placements of all components on the board are checked, any necessary placements that remain are placed manually and polarities of applicable components are checked and changed as per what is given in the AEGIS. The same changes are made in the assembly program to avoid the same occurrence in the rest of the batch. Components that are designated as DNP (Do Not Place) are also checked and finally, the solder paste information such as solder type, lot number, date of manufacture, and expiry are checked to ensure that the right solder paste has been used.
4. All these checks translate to notes, remarks, and checks on the AEGIS document, which can then be referred at later stages up to final inspection. If the job in consideration is a repeat job, it can be optimized to avoid any errors made in the first batch of production.
5. The board is then sent through reflow. Once reflowed, the board is extensively inspected under high magnification camera for quality of component placement, solder joints etc. yielded by SMT process.
6. Each section in the AEGIS is meant for FAI by a different team performing a different operation.

PNC has been able to reduce its lead time and increase customer satisfaction significantly and our personalized and successful FAI is a big factor contributing towards it. Further development to the FAI process is underway as much as it is needed to achieve better production yield over time for all the different types of PC Board assembly that are assembled at PNC.

PRINTED CIRCUIT ASSEMBLY TESTING

No single printed circuit assembly testing system will meet all the requirements of every manufacturing environment. PNC employees the three most commonly used testing methods for defect detection being Functional Test (FCT), In circuit Testing (ICT) and Flying probe testing. Each test method will have different results based on your test strategy.
Your testing strategy must be developed with consideration to many factors such as reliability, cost or functionality traits. The key here is to detect defective boards and catch issues prior to end usage. Some considerations like opens, shorts, resistance, capacitance, inductance, diode issues, detecting incorrect component values, functional failures, and parametric failures are a few things that need to be addressed before your test strategy is finalized. Below is a brief description of the three test methods that are performed at PNC.

Functional Circuit Test (FCT)
Functional Circuit Test (FCT)

PNC offers multiple pc board assembly testing services. The most commonly performed, non-automated, printed circuit assembly test for electrical performance is functional testing, whether it be a partial or a full test procedure. Variabilities include what is to be tested, what inputs/outputs are needed, what are the required results and what are the testing parameters. These parameters are pre-determined from our customer supplied test procedures. FCT not only verifies the functionality of the PCB, but can also determine any assembly defects.
FCT is best suited for smaller to medium size volumes which helps our customers save a considerable cost by eliminating the need to buy actual testing equipment such as Spectrum Analyzers, AC/DC power supplies, multi-meters, etc. Depending on the complexity of the functional test to be executed, a pogo pin test fixture may be fabricated to expedite the test for optimum test results making it error-free and robust.

In Circuit Test (ICT)

PNC’s biggest advantage to in circuit testing is that it can test for functionality as well as for printed circuit assembly defects. ICT is normally much faster than probe or functional testing as it makes connection to all the board’s test points at once using a clam shell bed of nails fixture. Interpreting the test results are normally very easy to identify shorts, opens, or a particular faulty component location. As a
pcb assembly contract manufacturer
speed, efficiency, and quick test results help ensure a quality printed circuit assembly.
Although there are advantages to ICT, we do find some disadvantages as well. The development of this fixture has a significant investment of time and money associated with it. To our customer base, the expense of the fixture and programming can only be recovered on boards being assembled in large volumes. In the event there are any revisions to the PCB, the layout would initiate changes to the fixture, thus resulting in a completely new fixture and the expenses associated with it.

Probe Test
Probe Test

Flying probe testing is a pre-programmed, automated system that controls two to six probes that maneuver (fly) around a printed circuit assembly to contact test points, checking nets, on both the top and the bottom of the board. Flying probe has a lower cost and minimal programming time for setup than ICT. The biggest advantage to probe testing is revisions/changes to the pcb assembly. There is no fixturing modification cost, only the programming need be adjusted.
Probe testing is slower than ICT, and best fits medium sized assembly runs, so for complex high volume production runs its not preferred or cost effective. Another disadvantage to flying probe testing is that is does not perform functional testing and is limited to detecting pcb assembly defects.