Tag Archives: Pga Capabilities

BGA-HDI

Better BGA routing on a Printed Circuit Board with High Density Interconnect

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One of the technologies that have allowed electronic products to shrink in size and provide increasingly higher performance is the ball grid array (BGA) IC package. The BGA allows higher density Printed Circuit Board layouts because of simple geometry. The number of pins that can be accommodated on the perimeter of a quad pack increases linearly with package size. The number of connections that can be accommodated on a BGA increases with the square of the package size. BGA packages now routinely exceed 1000 connections, and the ball pitch has shrunk from 1.0 mm to .8 mm to a growing number of devices now available in the micro-BGA format with a ball pitch of .65 mm, .5 mm and smaller.

The decrease in BGA ball pitch would not have been possible without the improvements in PCB fabrication. These improvements, collectively called High Density Interconnects or HDI, give companies like PNC the capability of creating traces as narrow as 0.0762 mm (3 mil) and vias with annual rings as small as .25 mm (10 mil) HDI PCB fabrication has given designers greater flexibility in routing BGA devices down to a pitch of .65 mm The HDI technology is essential for devices with ball pitches less than .65mm

Routing the hundreds of connections from a typical BGA is called BGA breakout, and it can be a major layout challenge. For this reason, many designers place the BGAs into the layout first and fan-out the connections from each pad to a stub trace. This allows the designer to adjust the routing of individual pins under the BGA without rerouting the entire Printed Circuit Board. Another reason the BGA should be placed first is that the BGA breakout will likely dictate the number of layers needed in the PCB stack-up.

The breakouts are typically a repeating pattern, with the traces for each row of balls around the perimeter routed similarly. Most BGA manufacturers will provide sample breakouts, and some high-end tools will automate this breakout process. Most BGAs use similar fanout approaches, the fanout differing only in the package specific routings for power and ground. With standard PC Board fabrication technology there really are not a lot of fanout options. Here is the typical approach used for BGAs with pitches down to .65 mm highlighting some of the advantages of PNC’s HDI fabrication technology

Routing the first perimeter row of the BGA is easy; the traces come straight out from the pads.

The traces for the second row pass between the pads of the first row. If the ball pitch is greater than .8 mm an HDI PCB fabricator with the capability of creating 3mm pitch traces can fit two 3mm traces with 3mm spacing between the pads in the outer row. This allows the first three perimeter rows of pads to be routed on the top layer.

Subsequent rows are routed using a feature called a dogbone. The dogbone has a pad at one end and a via at the other, separated by short trace. This prevents the via from wicking solder from the ball pad, starving the solder joint. It is also recommended to cover or “tent” the dogbone via with solder mask. The dogbone is typically oriented at 45 ° so that the via can be located in the center of each four pad grid. The via takes the signal trace to the next level where it is routed out between the other vias, similar to what was done on the top layer.

the following number of board layers typical are needed for each perimeter row of pads

board layers
board layers

This table demonstrates that using an HDI Circuit board fabrication process, even for a 1.0 mm or .8mm pitch BGA can result in the need for fewer signal layers, because two traces can be passed between each pad. The HDI fabrication process also allows the dogbones to be placed in line with the grid instead of diagonally, which allows two traces to pass between vias on the 2nd and 3rd layers

For smaller pitch devices PNC’s HDI fabrication techniques become essential. For ball pitch spacing of .65 mm and .5 mm the only way to create a fanout is using the 3 mil traces and 10.68 mill dia. vias allowed by HDI. The 3 mil trace and 3 mil trace spacing allows a single trace to just fit between .5 mm pitch pads.

The latest micro BGAs used in devices like phones and smartwatches have pitch spacing below .4 mm. The pitch spacing is so close that traces no longer fit between the pads. BGA breakout requires via in pad techniques, with the filled microvias routing the signals straight down and then out. Depending on the number of perimeter rows, blind and buried vias may also be needed.

If you are using a BGA in your design, using HDI design rules for fabrication can simplify the breakout and reduce the number of PCB layers needed. PNC engineers can help you understand what is possible with HDI Printed Circuit board fabrication.
The last thing to know about designing with BGAs is that process yield, and reliability are very process dependent. When selecting a
Pga Capabilities it pays to select PNC. PNC has the equipment and expertise to manufacture your most challenging BGA designs.

Motor Control EMI: AC Mains Conducted Emission

PCB Design,

We do not want our product to come back from testing to find that we have failed electromagnetic interference (EMI) or conducted emissions (CE) exams. Furthermore, we do not want these noise sources to degrade our products performance, so we need to understand the mechanisms of this noise and how to minimize it.

One of the most common failures is, AC mains conducted emission testing which is listed as IEC 61326-1:2005, Ed. 1 section 7 (CiSPR11:2003). The purpose of the conducted emissions test is to measure noise currents that exit the products ac power cord to be sure the currents are within the regulated limits. The most efficient method for the reduction of conducted emissions is to reduce them at their sources. In this section we will discuss the source of conducted Emission on AC mains and how we can minimize the emissions. In following section we will focus on workarounds for the system has failed pass the AC mains conducted emission test.


3 Wire system filer and safety connections

Rectifiers:

Fast recovery diodes snap off sharply and generate high frequency noise compared to slow recovery diodes. In order to reduce this undesirable noise generated in the turnoff of the diode, snubber circuits are generally placed in parallel with the diodes. The snubber circuit consists of a resistor in series with a capacitor that acts as a path to discharge the charge stored at the diode junction when the diode turns off. This tends to smooth the diode current waveform, thereby reducing high frequency spectral content. The high frequency current will circulate through the snubber circuit where the leads need be kept short and the elements placed very close to the diode. In doing this, you will reduce the current loop area and the emissions will be radiated from the loop.

 

Transformer:

Winding the coils on top of each other introduces a parasitic capacitance between the primary and secondary. This primary-to-secondary capacitance can introduce an undesired coupling that allows noise on the secondary side to be more easily coupled to the primary side. Once the noise is present on primary side, it passes out through the power cord and is measured as a conducted emission by the LISN, unless the power supply is inserted between the power cord and transformer. The efficiency of this coupling, due to the parasitic primary-secondary capacitance increases at higher frequencies. In order to reduce this coupling, there is need for a metallic shield between the primary and secondary coils. This is referred to as a Faraday shield. This shield should be connected to the primary side reference or neutral.

 

Switching devices:

Primary current begins to flow when a MOSFET(s) is turned on. The transformer primary current ramping to a peak value is determined by input voltage, motor phase inductance, switching frequency and duty cycle. This trapezoidal (or triangular) current waveform is characterized in the frequency domain by a spectrum at the switching frequency. The harmonics are determined by the relative squareness of the waveform and causes the primarily differential mode emission currents to circulate between the AC mains and the power supply input. This current waveform can also create common mode emissions, due to radiated magnetic fields when the current path defined on the PC board layout encircles a large physical area.

 

The spectral content of the noise that is produced by switching is directly dependent on the rise and fall times of pulses. The slow (high) rise and fall times are desirable from the standpoint of EMC. This causes the MOSFET to spend more time in its active region, which increases its power dissipation, therefore is an undesirable result from the standpoint of thermal consideration. Concurrently, there is an apparent tradeoff between reduction of noise spectral content that will contribute to conducted emissions and the thermal heating of the switching element and related efficiency of the switcher.

 

Wire Harness and System connections:

Noise current sources appear between live and neutral connections without reference to the earth connection. In circuits with a switching power supply or motor control, the RF emissions are dominated by interference developed across the DC link to the switching devices. Although there will be a bulk capacitor, the high di/dt through this capacitor will generate voltages at the harmonics of the switching frequency across its equivalent series impedance.

 

The coupling is dominated by the inter-winding capacitance of the isolating transformer, stator-rotor of the motor and system to the chassis. These capacitances are referred to earth, either directly or via the enclosure if this is conductive. A well shielded enclosure will minimize “leakage” of this capacitive coupling and hence reduced conducted emissions. Ideal connections for 2-wire and 3-wire system are shown in figure xx and xx.

2 Wire system filer and safety connections.bmp

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This article was written by Sam Sangani Jr., PNC Inc.’s Fellow Design Engineer. For additional information related to this or any other topic, you can reach Sam via e-mail at sam@pnconline.com.