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Minimizing Crosstalk in PC Board Layout

Minimizing Crosstalk in PC Board Layout

In this ongoing series on PCB layout from the design team at PNC, previous posts have looked at some of the initial steps to turn a circuit schematic into a manufacturable, reliable PCB. These posts have looked at  component placement, selecting appropriate trace widths, and BGA routing.   In this post we are going to take a deeper dive into methods for reducing crosstalk in the PCB design. After the power and ground have been routed, the next task is to route high speed signal traces, and the traces that could either generate or receive crosstalk.

 What is Crosstalk?

Crosstalk occurs when the signal on an aggressor trace on a PCB appears on a nearby victim trace, due to capacitive and inductive coupling between the two traces.  Typical aggressor signal traces are:

● High speed digital signals, especially clock signals
● Noise from switching power suppliers
● High frequency RF.

Victim signal traces, on the other hand, carry high impedance signals like op amp input lines or reset lines, or low impedance signals with long loops.   Low amplitude signals such as a sensitive analog measuring circuit traces are also susceptible.

Crosstalk occurs when aggressor trace and victim trace are close together and run in parallel for a distance.  The aggressor and victim(s) can be side to side on the same layer or on top of each other on adjacent signal layers. Coupling between traces on adjacent layers separated by just a thin section of laminate is called broadside coupling.

Minimizing Crosstalk in PC Board Layout
Minimizing Crosstalk in PC Board Layout






Printed Circuit Board Design guidelines to reduce crosstalk

There are several design rules to reduce crosstalk between signal traces.  Before applying these rules, the first step is to use the general guidelines described above to identify and flag any potential aggressor signal traces and their potential victims.

Since crosstalk occurs between two traces running in parallel, try to reduce the distance that the aggressor and victim traces run in parallel. Unfortunately, this may be difficult if the signals originate and terminate from the same locations.  To minimize broadside coupling try to orient the signal traces east-west on one layer and north-south on the second layer.

It is essential to have a broad contiguous ground plane directly under (or over) the signal layer.  A ground plane located between two signal layers can prevent broadside coupling. However, make sure that ground planes located on adjacent layers but not electrically connected do not overlap.  The overlapping ground planes separated by a dielectric form a capacitor, which can transmit noise from one ground plane to the other. This can defeat the purpose of separate ground planes if they were created to isolate the noisy elements of a circuit from the noise sensitive ones.

Increasing trce spacing

The most effective method of reducing crosstalk is to increase the spacing between the aggressor signal trace and the potential victim traces.  Like all electromagnetic radiation, electrical or magnetic coupling between the two traces drops with the square of the distance between them.  The amount of spacing required between the traces is dependent on the height of the traces above the ground plane.   The formula defining this relationship is from Douglas Brooks “Crosstalk Coupling: Single-Ended vs. Differential”   The coupling between two traces is proportional to:

Where S is the spacing between traces, and H is the distance from the trace to the ground plane.  Once H is defined by the lamination stack-up, the relative change in coupling can be easily plotted as a function of S.  Douglas Brooks looks in detail at the coupling between traces under several scenarios.  For those looking for some general guidance, a spacing of 5H is considered conservative.  The PC Board design team at PNC can assist designing a PCB stack up that will minimize the spacing needed between coupled traces, ensuring that crosstalk is minimized while maintaining routing density.

Finally, for very high speed digital signal traces, consider the use of differential pairs.  For many designers, the most common applications for a differential pair is for a high speed serial bus like USB, SATA, or HDMI.  The design rules for the layout of differential traces is beyond the scope of this post.

The most important part of reducing crosstalk in your PCB design is to first recognize in which signal traces crosstalk is likely to occur, then follow the guidelines above to minimize it.  PNC’s Printed Circuit Board designers have experience with high speed digital and RF circuits and can help you select the correct PCB layer stack-up and review your designs for areas where crosstalk is likely and suggest ways to minimize it. Request a design review from PNC today


Accelerate your New Product Development with rapid PCB assembly prototyping

The time from concept to prototype has accelerated remarkably in the past decade. 3D printed prototype components in a wide variety of materials are available in hours. Machined or sheet metal components are available from rapid prototype shops in only one or two days.

Prototype Printed Circuit Board Fabrication and assembly companies like PNC have followed this trend towards faster prototypes and can now provide complete assemblies in less time than ever before. PNC can fabricate and deliver a bare 10-12-layer PCB in just three days, and a simple double-sided board in just 24 hours.

However, even with the streamlining of PCB fabrication, the fully assembled PCBA is often the longest lead component in prototype designs primarily because of the sheer number and variety of passive and active components to be purchased and the demands of accurately placing and soldering those components. Sourcing the components on a typical PCBA BOM can take days in the best case and weeks in the worst case. Setting up and running the assembly job can add another few days, especially for double sided PCBs, and PCBs with a combination of surface mounted and through hole components.

Fortunately, there are some things that a product development team can do to reduce PCB assembly lead time.

First, do everything possible to reduce the impact of long component lead times. Plan to order the components as early as possible in the circuit design process. Deciding when to order components requires balancing the costs of scrapping some components as the design matures vs. the benefits of reducing the lead time for an assembled PCBA by days or weeks.

Second, reduce the time required to set up and build the prototypes by working with a full-service company like PNC. PNC has the capability to both fabricate the bare PCB and assemble the components. This means that the PCB fabrication team and assembly team can save time by working in parallel. While the PCBS are being fabricated, PNC’s engineers can create pick and place data, solder paste stencils and program the assembly equipment. When the PCBs are finished and the components arrive, everything is ready to begin assembly immediately.

The third way to save time with PCB prototypes is to minimize the number of PCB prototype iterations. Saving a full printed circuit board assembly prototype cycle is the most effective way to reduce the time from concept to mature design.

One way to reduce design iterations is by testing circuit designs as early in the design process as possible by building “Works Like” prototypes. “Works Like” prototypes are usually combinations of development kits, large one or two layer PCBs with larger SMT components that can be soldered by hand and various types of breadboards. In addition to testing the circuit, a “Works Like” prototype gives software developers an early platform to start developing code and debugging the circuit design. The result of testing early with rough prototypes is that you fix problems before you have invested the time in the full layout and prototyping process.

In parallel, the mechanical engineers can optimize cable routing and connector placement by printing 3D models of the PCBs, then epoxying actual connectors to the board model. This is an effective way to quickly try different options for cable routing using actual cables and connectors, since it is difficult to simulate the way actual cables behave with CAD software.

Experienced electrical engineers know that it is often poor connector access or cable interference that drive Printed Circuit Board layout redesigns as often as issues with actual circuit performance.

Once the circuit has been tested with the “Works-Like” prototype, and the board layout has been tested with 3D printed models, the last way to save time is to work closely with the PCB manufacturer to make sure that the PCB fabrication files are clean and complete, and that the BOM is accurate and matched with the circuit and layout to avoid placement mistakes.

This is another reason to select a full-service prototype pcb manufacturer like PNC. PNC can be a partner during the layout and design process, though fabrication and assembly ensuring the final design can be translated into a working prototype in the least possible time.